? 2001 fairchild semiconductor corporation ds009174 www.fairchildsemi.com october 1986 revised june 2001 dm74als652 octal 3-state bus transceiver and register dm74als652 octal 3-state bus transceiver and register general description this device incorporates an octal transceiver and an octal d-type register configured to enable transmission of data from bus to bus or internal register to bus. this bus transceiver features totem-pole 3-state outputs designed specifically for driving highly-capacitive or rela- tively low-impedance loads. the high-impedance state and increased high level logic drive provide this device with the capability of being connected directly to and driving the bus lines in a bus organized system without need for interface or pull-up components. they are particularly attractive for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. the registers in the dm74als652 are edge-triggered d-type flip-flops. on the positive transition of the clock (cab or cba), the input data is stored into the appropriate register. the cab input controls the transfer of data into the a register and the cba input controls the b register. the sab and sba control pins are provided to select whether real-time data or stored data is transferred. a low input level selects real-time data and a high level selects stored data. the select controls have a ?make before break? configuration to eliminate a glitch which would nor- mally occur in a typical multiplexer during the transition between stored and real-time data. the enable (gab and g ba) control pins provide four modes of operation: real-time data transfer from bus a to b, real-time data transfer from bus b to a, real-time bus a and/or b data transfer to internal storage, or internal stored data transfer to bus a and/or b. features switching specifications at 50 pf switching specifications guaranteed over full tempera- ture and v cc range advanced oxide-isolated, ion-implanted schottky ttl process 3-state buffer-type outputs drive bus lines directly independent registers and enables for a and b buses multiplexed real-time and stored data ordering code: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. connection diagram order number package number package description dm74als652wm m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide dm74als652nt n24c 24-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 dm74als652 function table h = high logic level l = low logic level x = don ? t care (either low or high logic levels, including transitions) h/l = either low or high logic level excluding transitions = positive-going edge of pulse note 1: the data output functions may be enabled or disabled by various signals at the g and dir inputs. data input functions are always enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. note 2: select control = l; clocks can occur simultaneously select control = h; clocks must be staggered in order to load both registers. logic diagram inputs data i/o (note 1) operation or function gab g ba cab cba sab sba a1 thru a8 b1 thru b8 xh h/l x x input not specified store a, hold b lxh/l x x not specified input store b, hold a lh x x input input store a and b data l h h/l h/l x x input input isolation, hold storage l l x x x l output input real-time b data to a bus l l x h/l x h output input stored b data to a bus h h x x l x input output real-time a data to b bus hh x x input output stored a data to b bus hh x (note 2) x input output store a in both registers ll xx (note 2) output input store b in both registers h l h or l h or l h h output output stored a data to b bus and stored b data to a bus
3 www.fairchildsemi.com dm74als652 absolute maximum ratings (note 3) note 3: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ? recommended operating conditions ? table will define the conditions for actual device operation. recommended operating conditions note 4: = with reference to the low-to-high transition of the respective clock. electrical characteristics over recommended free air temperature range note 5: for i/o ports the 3-state output currents (i ozh and i ozl ) are included in the i ih and i il parameters. supply voltage 7v input voltage control inputs 7v i/o ports 5.5v operating free-air temperature range 0 c to + 70 c storage temperature range ? 65 c to + 150 c typical ja n package 44.5 c/w m package 80.5 c/w symbol parameter min nom max units v cc supply voltage 4.5 5 5.5 v v ih high level input voltage 2 v v il low level input voltage 0.8 v i oh high level output current ? 15 ma i ol low level output current 24 ma f clk clock frequency 0 40 mhz t w pulse duration, clocks low or high 12.5 ns t su data setup time, a before cab or 10 ns b before cba (note 4) t h data hold time, a after cab or 0 ns b after cba (note 4) t a free air operating temperature 0 70 c symbol parameter test conditions min typ max units v ik input clamp voltage v cc = min, i i = ? 18 ma ? 1.2 v v oh high level v cc = 4.5v to 5.5v i oh = ? 0.4 ma v cc ? 2 output voltage v cc = min i oh = ? 3 ma 2.4 3.2 v i oh = max 2 v ol low level v cc = min i ol = 12 ma 0.25 0.4 output voltage i ol = 24 ma 0.35 0.5 v i ol = 48 ma 0.35 0.5 i i input current at maximum v cc = max i/o ports, v i = 5.5v 100 a input voltage control inputs, v i = 7v 100 i ih high level input current v cc = max, v i = 2.7v, (note 5) 20 a i il low level v cc = max, control inputs ? 200 a input current v i = 0.4v (note 5) i/o ports ? 200 i o output drive current v cc = max, v o = 2.25v ? 30 ? 112 ma i cc supply current v cc = max outputs high 47 76 outputs low 55 88 ma outputs disabled 55 88
www.fairchildsemi.com 4 dm74als652 switching characteristics over recommended operating free air temperature range (note 6) note 6: these parameters are measured with the internal output state of the storage register opposite to that of the bus input. symbol parameter conditions from (input) min max units to (output) t plh propagation delay time v cc = 4.5v to 5.5v, cba or cab 10 30 ns low-to-high level output c l = 50 pf, to a or b t phl propagation delay time r 1 = r 2 = 500 ? ,cba or cab 517ns high-to-low level output t a = min to max to a or b t plh propagation delay time a or b to 518ns low-to-high level output b or a t phl propagation delay time a or b to 312ns high-to-low level output b or a t plh propagation delay time low-to-high level output sba or sab 12 35 ns (with a or b low) (note 6) to a or b t phl propagation delay time high-to-low level output sba or sab 6 20 ns (with a or b low) (note 6) to a or b t plh propagation delay time low-to-high level output sba or sab 6 25 ns (with a or b high) (note 6) to a or b t phl propagation delay time high-to-low level output sba or sab 5 20 ns (with a or b high) (note 6) to a or b t pzh output enable time g ba to 317ns to high level output a t pzl output enable time g ba to 518ns to low level output a t phz output disable time g ba to 110ns from high level output a t plz output disable time g ba to 216ns from low level output a t pzh output enable time gab to 622ns to high level output b t pzl output enable time gab to 618ns to low level output b t phz output disable time gab to 110ns from high level output b t plz output disable time gab to 216ns from low level output b
5 www.fairchildsemi.com dm74als652 physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m24b
www.fairchildsemi.com 6 dm74als652 octal 3-state bus transceiver and register physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n24c fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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